6 research outputs found

    On the Scalability of Data Reduction Techniques in Current and Upcoming HPC Systems from an Application Perspective

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    We implement and benchmark parallel I/O methods for the fully-manycore driven particle-in-cell code PIConGPU. Identifying throughput and overall I/O size as a major challenge for applications on today's and future HPC systems, we present a scaling law characterizing performance bottlenecks in state-of-the-art approaches for data reduction. Consequently, we propose, implement and verify multi-threaded data-transformations for the I/O library ADIOS as a feasible way to trade underutilized host-side compute potential on heterogeneous systems for reduced I/O latency.Comment: 15 pages, 5 figures, accepted for DRBSD-1 in conjunction with ISC'1

    PIConGPU simulation settings for TWEAC

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    The input sets of the simulations as used in the publication "Circumventing the Dephasing and Depletion Limits of Laser-Wakefield Acceleration" by A. Debus et al. . The input sets include TWEAC scenarios, the LWFA scenario and the laser-propagation scenario of Appendix D. The src-directories include custom additions to the PIConGPU source code. The simulations were run using the beta-rc6, 0.3.1, and 0.4.0 releases of PIConGPU (see DOI: 10.5281/zenodo.591746). The input sets are shown according to the respective PIConGPU version used in the original simulation. However, for running the simulations we recommend adapting the input sets to the 0.4.0 release

    Clamped annular plate under a concentrated force.

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